1. Field of the Invention
The present invention relates to a digital receiver structure suitable for a software-defined radio platform.
2. Brief Description of the Related Technology
Software-defined radio (SDR) is a collection of hardware and software technologies that enable reconfigurable system architectures for wireless networks and user terminals. SDR provides an efficient and comparatively inexpensive solution to the problem of building multi-mode, multi-band, multi-functional wireless devices that can be adapted, updated or enhanced by using software upgrades. As such, SDR can be considered an enabling technology that is applicable across a wide range of areas within the wireless community.
Handheld digital receiver cost reduction and time-to-market improvement call for software defined radio (SDR) implementation. To be viable in portable handheld devices, SDR needs to be low power. SDR low cost and low power requirements implies:                reactive multi-mode operations: the receiver should be able to be configured to detect, possibly concurrently, transmission according to a multitude of communication standards. When those transmissions are detected, they must be decoded.        scalability: multiple versions of the platform, matching demand and silicon process technology evolution, must be derived from an initial, scalable design.        programmability and retargetability: the development time to deploy an application based on a SDR platform must be minimized. This is only possible by implementing integrated platform-instantiation and application-mapping flows based on high-level languages.As programmability and energy efficiency must be carefully traded off to maintain energy efficiency at the level required for mobile device integration, programmability may only be introduced where its impact on the total average power is sufficiently low or at those places where the resulting extra flexibility can be exploited to yield an average energy gain through better matching of the system behavior to the utilization and the environment.        
State-of-the-art solutions tackle multiple standards and future-proof SDR platforms with e.g.:                master-slave general purpose processor (GPP)—digital signal processing (DSP) with multiple radio interface,        single or homogeneous multi-core System on Chip (SoC),Power consumption is tackled at computer architecture and/or circuit level, but not at system level (except for dynamic power management).        
Many different architecture styles have already been proposed for SDR. Most of these are designed keeping in mind the most important characteristics of wireless physical layer processing: high data level parallelism (DLP) and data flow dominance. For the first characteristic, hybrid VLIW (Very Long Instruction Word) and vector/SIMD (Single Instruction/Multiple Data) architectures are often considered to exploit the data level parallelism with limited instruction fetching overhead. However, directly mapping C-code, even with high DLP, on such architectures remains a challenge for the compiler. The second characteristic is exploited by fine-grain reconfigurable arrays (FGA) and coarse grain reconfigurable arrays (CGA). The main bottleneck of the FGAs is the high interconnect cost that hampers their scalability and that yields significant energy overhead. CGAs improve on this point proposing less but more complex functional units.
Although several proposals (see e.g. also ‘Finding the optimum partitioning for multi-standard radio systems’, Bluethgen, Proc. Int'l SDR Technical Conference, November 2005) have contributed significantly to the integration of SDR in personal communication handhelds, none of the proposed platforms has the required features to enable reactive radio. Specifically, no solution has been proposed for multi-mode reactivity. Also their computing power at reasonable energy-efficiency is still too limited to exploit multiple signalling dimensions. This is mainly due to the fact that only the characteristics of the modulation/demodulation baseband processing are considered. In practice, a radio standard implementation also contains functionalities for medium access control and, in case of burst-based communication, signal detection and time synchronization. The desired characteristic of data level parallelism (DLP) does not hold for medium access control (MAC) processing which is, by definition, control dominated and, hence, better fits on RISC processors. Besides, packet detection and coarse time synchronization of burst-based transmission have a significantly higher duty cycle than packet modulation and demodulation. They hence require another flexibility/efficiency trade-off.
One possible application of such a reactive digital receiver relates to a mechanism for a hand-over operation between two base stations or access points of a mobile terminal comprising such receiver. The base stations are each arranged to cover a particular coverage area or cell. The coverage areas are partly overlapping, such that the arrangement supports a cellular network.
A hand-over can be a hard hand-over whereby the mobile terminal is (physically) connected to only one base station at a time, so that the connection to the current base-station must be terminated before the connection to the new base-station can be achieved. This implies an unconnected period (a “break”) during the hand-over. The hard hand-over is also referred to as “break-before-make”. On the contrary, a soft hand-over is a hand-over mechanism where the mobile terminal can be connected to two base-stations at the same time. This is also called “make-before-break”.
With seamless hand-over is meant a hand-over going by unnoticed from a user perspective, i.e. without interruption of ongoing services. Seamless hand-over does not necessarily imply soft-handover (though soft-handover makes seamless handover easier).
Soft handover is possible between two 3G base stations operating at the same frequency and distinguished by two different CDMA scrambling codes. In the 3G cellular systems, a scrambling code, associated to each base station, is super-imposed to the usual CDMA code that separates the mobile terminals. One mobile terminal can make use of the scrambling codes to receive the signals of two base stations simultaneously with a single front-end.
Seamless hard handover can be achieved through synchronization of the base stations. Based on this synchronization the base station allows the terminal to scan neighboring cells during a limited time and if needed it triggers a hard hand-over that can happen relatively fast. This technique is not possible for hard hand-over between different network technologies on one hand, and requires complex network synchronization for a single network on the other hand.
For 802.11 wireless LAN, there is the possibility of connecting one terminal to multiple access points at the same time, through a time division scheme using the power save mechanism provided by the 802.11 protocol. This technique is useful for protocols and applications where the protocol provides a power-save feature with a time constant smaller than the latency bound of the application.
In EPO patent application EP1328066-A2 a semiconductor device is disclosed that is functionally divided into blocks. The power supply systems of the blocks are divided into a non-controlled power supply group in which power is always on and a cascade of controlled power supply groups in each of which groups a supply of power can be turned on/off independently, but in a chained way. This means that the power of a given block is controlled by the predeceasing block in the cascade. The blocks that are not necessary for performing a specific piece of processing are not supplied with power. For example, the decoding block is only switched on when the processing in the preceding demodulation block has been done. The division into various blocks is purely functional and does not take into account any consideration regarding the actual static or dynamic power of the blocks, their duty cycle, nor their trade-off between energy efficiency and flexibility. By construction, the higher the hierarchical level of a block, the higher the duty cycle is.
U.S. Pat. No. 6,978,149-B1 relates to a transceiver the receiver part of which is switchable between a sleep mode and an active mode. A control circuit is provided for switching the receiver from sleep mode to the active mode when an information signal to be received is detected. The control circuit takes a decision to switch based on a power level of the information signal, the power level being represented by a received signal strength indicator (RSSI) signal. Here again, a cascaded activation chain is foreseen, with a purely functional partitioning.
It is desirable to have a scalable, energy-efficient digital receiver structure enabling spectrum environment awareness and gradual system wake-up in response to incoming radio transmissions.